The subject invention pertains to a metal-semiconductor diode clamped complementary field effect transistor and corresponding integrated circuits. The method and device of the subject invention can be utilized with respect to insulated gate field effect transistors (IGFET). The circuitry of the subject invention can utilize Schottky barrier drains and/or sources to enhance performance. In particular, the design of these circuits can allow for a reduction in circuit surface area in comparison with comparable existing circuits. In a specific application, the subject invention can be applied to essentially all integrated circuits utilizing complementary metal oxide silicon (CMOS) technology. CMOS circuits, such as microprocessors, dynamic random access memory (DRAM) chips, random access memory (RAM) chips, digital signal processors (DSP) chips, and mixed signal integrated circuits, produced in accordance with the subject invention can also have reduced susceptibility to latch-up. In addition, the subject CMOS circuit designs can reduce the number of metal interconnects needed for interconnection with other circuits.
As mentioned, circuits in accordance with the subject invention can have reduced susceptibility to latch-up, where latch-up can cause a undesirable large current flow from supply to ground. Typically, the latch-up involves parasitic n+-p-substrate-n-well and p+-n-well-p-substrate bipolar junction transistors. Accordingly, the susceptibility to latch-up can be reduced by decreasing the current gains of the parasitic bipolar junction transistors.
Schottky barriers and their RF applications have been studied extensively (Sharma, B. L. [1984] xe2x80x9cMetal-Semiconductor Schottky Barrier Junctions and Their Applications, New York; Mollenkopf, S., G. M. Rebeiz [1994] xe2x80x9cA 22 GHz MIC active receiver/radiometerxe2x80x9d IEEE MTT-S Int. Microwave Symp. Dig. 3:1347-1350). An insulated gate field effect transistor using Schottky barrier contacts for source and drain was first proposed in 1968 (Lepselter, M. P., S. M. Sze [1968] xe2x80x9cSB-IGFET: An insulated-gate field-effect transistor using Schottky Barrier contacts as source and drainxe2x80x9d IEEE Trans. Electron Devices 56:1400-1402). Recently, Schottky contacts (Milanovic, V., M. Gaitan, J. C. Marshall, M. E. Zaghloul [1996] xe2x80x9cCMOS foundry implementation of Schottky diodes for RF detectionxe2x80x9d IEEE Trans. Electron Devices 43:2210-2214) and MOS transistors using a Schottky barrier as a drain (Huang, F.-J., K. K. O [1997] xe2x80x9cMetal-oxide semiconductor field-effect transistors using Schottky Barrier Drains (SBDR)xe2x80x9d Electron. Lett. 33(15):1341-1342) were studied using foundry CMOS processes. The transistors suffer from high drain to substrate leakage current and low breakdown voltages (Huang, F.-J., K. K. O [1997], supra; Yu, A. Y. C., E. H. Snow [1968] xe2x80x9cSurface effects on metal-silicon contactsxe2x80x9d J. Appl. Phys. 39(7):3008-3016) as well as reduced drain currents (Huang, F.-J., K. K. O [1997], supra). In NMOS RF amplifiers with a tuned load, especially when the supply voltage is low, it is desirable for drain nodes of some transistors to swing below GND to increase the output power level. Unfortunately for integrated RF amplifiers, this forward-biases the p-substrate-to-n+-drain junction(s) and may trigger latch-up. A similar requirement exists for RF switches.
The subject invention relates to a metal-semiconductor diode clamped semiconductor device and method for producing such device. A specific embodiment of the subject invention utilizes one or more Schottky barriers at, for example, the drain and/or source of at least one transistor of a field effect transistor integrated circuit. The use of one or more Schottky barriers is useful for reducing the susceptibility of latch-up for circuits having two opposite type transistors, i.e., two opposite polarity carriers, in which the two transistors are in close enough proximity to experience latch-up. The subject invention is applicable to insulated gate field effect transistors (IGFET). For example, the subject invention can be utilized with complementary metal oxide silicon (CMOS) devices. Advantageously, the manufacturing process required to produce the subject devices can require minimal adjustments to the standard processing steps used, for example, in conventional IGFET and/or CMOS processing.
The subject invention can enable the production of IGFET and/or CMOS circuits with a reduced area. This decreases the cost of integrated circuits and allows more functions to be integrated in an integrated circuit. Advantageously, the structure of the subject invention can be implemented within existing IGFET and/or CMOS technology processes and is also consistent with the trend for future IGFET and/or CMOS technology processes.